The present invention relates generally to the field of semiconductor memory devices, and more particularly to non-volatile memories. Still more particularly, the invention relates to electrically erasable and programmable non-volatile memories such as Flash memories.
Typically, Flash memories offer the possibility of writing data per single Bytes or words (of two or multiple of two Bytes). On the contrary, when even a single data Byte or word stored in the memory is to be modified, it is necessary to erase the information stored in the whole memory or, at the best, in a whole memory sector containing such Byte or word.
This is a significant disadvantage of Flash memories. In fact, even if memory sectors are provided, the minimum memory sector size that can be practically achieved, at a reasonable cost in terms of semiconductor chip area, is of some Kbytes. This means that when a given data Byte or word belonging to a given memory sector is to be modified, the whole memory sector, that is some Kbytes of memory space, must be erased and then rewritten.
This limits the otherwise highly desirable use of Flash memories in those applications which require often to modify single data Bytes or words.
In the co-pending European Patent Application No. 00830553.4, filed on Aug. 2, 2000 in the name of the same Applicant of the present application, and incorporated herein by reference, a semiconductor memory is described which overcomes the above drawback, offering the possibility of being not only written, but also erased per single data words.
Briefly, let a two-dimensional array of memory cells be considered, which can be the whole memory matrix or a memory sector of a Flash memory. The memory cells are conventionally arranged in rows (word lines) and columns (bit lines).
Instead of forming all the memory cells of the two-dimensional array within a single doped semiconductor region, normally of P conductivity type for N-channel memory cells, formed in turn in an N conductivity type well, a plurality of P type doped semiconductor regions are provided in the N type well. The P type doped semiconductor regions of said plurality are in the form of stripes which extend side by side transversally to the rows, under the columns.
The columns are thus grouped in packets. Memory cells belonging to columns of a same column packet are formed in a same one of said P type doped semiconductor stripes. Thus, the set of memory cells of each row is subdivided into a plurality of sub-sets of memory cells, each sub-set containing those memory cells which are formed in a same one of said P type doped semiconductor stripes.
While in writing a Byte granularity is maintained, by providing circuitry capable of selectively biasing in erasing the P type doped semiconductor stripes and rows, it is thus possible to selectively erase only the memory cells belonging to one of said sub-sets of a selected row.
The elementary memory block that can be individually erased is thus formed by one of said sub-sets of memory cells defined by the intersection of a given row with one of said P type doped semiconductor stripes. Said elementary memory block, also referred to as xe2x80x9cmemory pagexe2x80x9d, can for example contain eight, sixteen, thirty-two or sixty-four memory cells, depending on the width of the doped semiconductor stripes.
In the memory described above, which in the following will be referred to as xe2x80x9cpage Flashxe2x80x9d, all the bits of a given memory page or word are physically adjacent to each other, being formed in a same P type doped semiconductor stripe. On the contrary, in a conventional Flash memory the bits of a given memory word are topologically spaced apart from each other. For example, let a Flash memory be considered having a memory sector made up of 256 rows and 2048 columns, with memory locations of the width of a sixteen bit word. When a given memory location is selected, one row and sixteen columns of the memory sector are selected. The selected sixteen columns are spaced apart from each other of (2048/16)=128 columns. In other words, since in a conventional Flash memory the memory sector dimension is much higher than that of a column packet in the page Flash, the former allows a much better spatial distribution the bits making up each memory word than the latter.
Due to this, a page Flash memory is affected by a problem in the writing (programming) operation. As known, Flash memory cells are programmed by means of the CHE (xe2x80x9cChannel Hot Electronsxe2x80x9d) physical mechanism, producing charge carriers of sufficiently high energy to overcome the potential barrier of the dielectric interposed between the substrate and the floating gate, so as to charge the latter. To trigger such a mechanism, current is forced through the memory cells"" channel by applying a high drain and a high control gate voltage, with source grounded, while the memory cells"" bulk (substrate) is biased at a voltage equal to ground or negative to increase efficiency. It occurs that charge carriers are injected into the substrate from a region of the cells"" channel near to the drain thereof. The injected carriers give rise to a substrate current, that causes a voltage drop between the carriers injection region and the region of the substrate where the substrate bias voltage is applied (substrate contact). Such a voltage drop modifies the effective biasing of the memory cell.
In particular, the farther the memory cell to be programmed from substrate contact, the higher the voltage drop caused by the substrate current, and the less efficient the programming action. Consequently, for a fixed programming pulse length, the resulting memory cell threshold voltage comes to depend on the memory cell position within the memory word.
Additionally, for a superposition of effects, the voltage drop in the substrate at a given point (for example, in correspondence of a memory cell) is also affected by the voltage drop induced by the other memory cells which are simultaneously submitted to programming. So, the voltage drop is higher the higher the number of memory cells programmed in parallel and the shorter the distance between the memory cells to be programmed.
As a consequence, the effect described above depends also on the kind of logic information to be written in the memory word, that is, assuming that a logic xe2x80x9c0xe2x80x9d corresponds to a written cell, on the number of xe2x80x9c0xe2x80x9ds contained in the data word to be programmed, and on the distribution of said xe2x80x9c0xe2x80x9ds within the data word.
In order to limit the effects of the voltage drop in the substrate, it would be necessary to limit the number of memory cells that can be programmed simultaneously, and/or to set the memory cells to be programmed in parallel spatially apart from each other.
Clearly, the first solution is highly undesirable, since it lengthens the programming time of the memory matrix.
A page Flash, in which as discussed all the bits of any memory word are physically adjacent, is particularly affected by the above mentioned problem, because the distance between the memory cells (bits) to be programmed in parallel is quite small (equal to the pitch of a single memory cell along a row) compared to the distance in a conventional Flash memory.
In view of this state of the art, it is an object of the present invention to provide a memory structurally and functionally adapted to overcome at least the above mentioned problems.
According to the present invention, such an object is achieved by a non-volatile, electrically alterable semiconductor memory, comprising at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection means for selecting columns among said plurality of columns, and a write circuit for simultaneously writing a first number of memory cells, comprising:
a plurality of doped semiconductor regions extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased;
a plurality of column packets each one containing a second number of columns, said second number being equal to or higher than the first number, memory cells belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed,
said column selection means being such that, within each column packet, columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.